报告摘要：
After a brief review of integrated circuit development trends, special attention is given to MOSFET scaling over the years and today’s challenges, including the issues of power consumption, process parameter variation, short-channel effect etc., are described. The importance of strained Si methods for enhancing MOSFET performance and of high-k metal gate for reducing power consumption is discussed. New device structures and processes are presented and considered as possible solutions for 22nm/16nm CMOS technologies and beyond. At the end of my talk, I would like to share some insights and observations based on my own practice of innovations/inventions.

报告人简介：
Dr. Huilong Zhu is Chief Scientist of IC Advanced Process R&D Center, the Institute of Microelectronics of Chinese Academy of Sciences, and is responsible for advanced CMOS technology research.
Dr. Zhu obtained his B.S. in 1982 in physics at USTC and his Ph.D in 1988 in physics at the Beijing Normal University, Beijing, China. He worked at Argonne National Laboratory in 1990-1992 (Visiting Scholar), University of Illinois at Urbana-Champaign in 1992-1996 (Visiting Assistant Professor), Digital Equipment Corporation in 1996-1998 (Principal Engineer), Intel in 1998-2000 (Senior Engineer), and IBM in 2000-2009 (Advisory Engineer). He was an IBM Corporate Leading Inventor and an IBM Master Inventor. He is co-inventor of Dual Stress Liner Technique and Stress Proximate Technique, which have been widely used to enhance CMOS performance. He is also co-inventor to use recessing gate to enhance stress in the channel of a strained MOSFET, which is applied, as a key technology, to high-k metal gate CMOS products. Dr. Zhu has obtained 175 issued US patents and published over 40 technical papers.